It's coincidence. The change that causes a GPF when the APIC space overlaps with SMM space was an undocumented change when Sandy Bridge was rolled out. So some engineers at Intel may have had an inkling that something could happen there, but at the same time, Sandy Bridge was the first chip with an on-die memory controller, so the engineer assigned to the new implementation could have just been more diligent in thinking through failure scenarios.
Are AMD's (or other non-Intel shops') CPUs vulnerable to this remap gimmick as well - or, is it specific to Intel's circuitry? (Sorry, I can't read the slides at present.)
Sandy Bridge was the first Intel chip to have on-die memory controller and on-die GPU, but most of its predecessors from the Nehalem/Westmere microarchitecture had on-die memory controllers.
